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GENERAL DESCRIPTION
The W536XXXT, a member of ViewTalk family, is a high-performance 4-bit micro-controller (uC) with built-in speech unit, melody unit and 64seg * 32 com LCD driver unit which includes internal regulator,pump circuit and dedicated two pages LCD RAM. The 4-bit uC core contains dual clock source, 4-bit ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and 8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM) , is capable of expanding to 512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation. It is ideal for games, educational toys, remote controllers, watches, clocks and other application products which incorporate both LCD display and speech.
TM
Body
Voice I/O pad
W536030T
30 sec 4I/O,4I (RA/RD)
W536060T
60 sec 4I/O, 8I (RA/RC/RD)
W536090T
90 sec
8I/O, 8I , 8O (RA/RB/RC/RD/RE/RF)
W536120T
120 sec
8I/O, 8I, 8O (RA/RB/RC/RD/RE/RF)
WDT Y Y Y Y disable/Enable (Mask Option) Sub-clock Y Y Y Y RC/XTAL mode (Mask Option) RD port shared as Y(1) Y(1) N N (2) serial bus (Mask Option) Tri-state serial bus Y Y Y Y (Mask Option) ( 3) Cascaded Voice Y(1) Y(1) N Y ROM through serial bus (2) (1) Share 3 pads of RD port (RD1/RDP, RD2/SPDATA and RD3/WRP) (2) Dedicate serial bus 3 pads (RDP, SPDATA and WRP) to interface with W55XXX. Cascaded Voice ROM can help user to expand voice up to 512 sec by W55XXX chip. (3) Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this mask option is disabled to get minimum power consumption in general.
FEATURES
* Operating voltage: 2.4 volt ~ 5.5 volt * Watch dog disabled/enabled by mask option * Dual clock operating system - Main clock with RC/Crystal (400 KHz to 4 MHz) - Sub-clock with 32.768 KHz RC/Crystal by mask option
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Publication Release Date: Sep 2000 Revision A7

* Memory - Program ROM (P-ROM): 64K x 20 (ROM Bank0, 1, 2, 3, 4, 5, 6) - Data RAM (W-RAM): 1.4K x 4 bit (RAM Bank 0 is 896 nibbles from 0:000~0:37F and 0:380~0:3FF are mapped to special register. RAM Bank F is 512 nibbles from F:200~F:3FF either data RAM or dedicated to script kernel ) - LCD RAM (L-RAM): 512 x 4 bit x 2 pages (RAM Bank1, 2 from 200~3FF) * Maximum 24 input/output pads - Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external memory W55XXX interface @W536030T/060T) - Ports for output only: 8 pads (RE & RF port; W536090T/120T available only) - Ports for Input/output: 8 pads (RA and RB port; RB port is available for W536090T/W536120T only) * Power-down mode - Hold mode (except for 32kHz oscillator) - Stop mode (including 32kHz oscillator and release by RD or RC port) * Eight types of interrupts - Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody ) - Three external interrupts (Port RC, RD, RA) * One built-in 14-bit clock frequency divider circuit * Two built-in 8-bit programmable countdown timers - Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected - Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0 * Built-in 18/14-bit watchdog timer for system reset. * Powerful instruction sets * 8-level subroutine (including interrupt) nesting * LCD driver unit capability - VLCD higher than (VDD-0.5V) - Built-in voltage regulator to V2 pad - 64 seg x 32 com - 1/32 or 1/16 duty, 1/5 or 1/4 bias, internal pump circuit option by special register - COM24~ 31 and SEG40~63 can be shared as general input/output by special register - Either uC ROM or voice ROM used as LCD picture * Speech function - Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030T/060T/090T/120T based on 5 bits MDPCM algorithm - Voice ROM (V-ROM) available for uC data or LCD picture data. - Maximum 8*256 Label/Interrupt vector (voice section number) available - Provide two types of speech busy flag to either each GO or each trigger - Maximum up to 16M bits speech address capability interface with external memory W55XXX through serial bus. * Melody function - Provide 1K notes (22bits/note) dedicated melody ROM - Provide two types of melody busy flag to uC either each note or each song - Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7 - Tremolo, triple frequency and 3 kinds of percussion available - Maximum 31 songs available * Can mix speech with melody * Multi-engine controller * Direct driving speaker/buzzer or DAC output * Chip On Board available -2Publication Release Date:Sep 2000 Revision A7

BLOCK DIAGRAM
SEG0~63
COM0~31
V3,V4,V5,V6
V2
DH1,DH2
RAM 1.4K*4Bit
LCD DRIVER
VDD VLCD PUMP & REGULATOR VSS
PORT RA ACC TONE
RA0~3
ROM
64K*20Bit ALU
PORT RB
RB0~3
PORT RC
RC0~3
PORT RD PC Special Register IEF STACK (8 Levels) HCF FLAG1 LPX0 LPX4 HEF SPC PM0 LPX1 LPX5 PEF MLD MR0 LPX2 LPY0 EVF PORT RF FLAG0 PSR0 LPX3 LPY1 SPC_busy SPC_play LPXY Shared_ROM Data Speech MDPCM core Parallel to Serial
RD0~3
PORT RE
RE0~3
RF0~3 WRP RDP SPDATA VDDA VSSA ROSC
VSSP Timer 0 Timer 1 Interrupt ,Hold & Stop Control Voice ROM (1M /2M/3M/4M bits) MLD_busy MLD_play Dual Tone melody (1K notes) PWM/DAC Mix Block PWM1/DAC PWM2 VDDP
Watch Dog
Divide
Timing Generator
TEST
RES
XIN XOUT X32I X32O
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Publication Release Date:Sep 2000 Revision A7

PAD DESCRIPTION
SYMBOL XIN/RXIN I/O I FUNCTION Input pad for main clock oscillator. It can be connected to crystal when crystal mode is selected (SCR0.2=1), otherwise connect a resistor to VDD to generate main system clock while RC mode is selected (SCR0.2=0 and default). Oscillator can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External capacitor connects to start oscillation while crystal mode Output pad for oscillator which is connected to another crystal pad when in crystal mode. External capacitor connects to start oscillation when in crystal mode. 32.768 KHz crystal input pad or external resistor node 1 by mask option. External 15~20pF capacitor connects to get more accurate clock when in crystal mode. 32.768 KHz crystal output pad or external resistor node 2 by mask option. External 15~20pF capacitor connects to get more accurate clock when in crystal mode. General Input/Output port specified by PM1 register. If output mode is selected, PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option. Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special register is set to logic 1. An interrupt source. General Input/Output port specified by PM2 register. If output mode is selected, PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option. Initial state is input mode (W536090T /W536120T only.) 4-bit schmitter input with internal pull high option specified by PM3 register bit 2. Each pad has an independent interrupt capability specified by PEFL special register. Interrupt and STOP mode wake up source. RC0 is also the external event counter source of Timer1. (W536060T/090T/120T only.) 4-bit schmitter input port with internal pull high option specified by PM3 register bit 3. Each pad has an independent interrupt capability specified by PEFH special register. Interrupt and STOP mode wake up source. RD1~3 will be shared as the external memory W55XXX interface pads while RD port shared as serial bus mask option is enabled @W536030T/060T. Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving capability option. (W536090T/120T only) Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving capability option. (W536090T/120T only) System reset pad, active low with internal pull-high resistor. Test pad. Active high with internal pull low resistor. -4Publication Release Date:Sep 2000 Revision A7
XOUT
O
X32I/RSUB1
I
X32O/RSUB2
O
RA0 ~ RA3/TONE
I/O
RB0 ~ RB3
I/O
RC0 ~ RC3
I
RD0 RD1/RDP RD2/SPDATA RD3/WRP (4) RE0~RE3
I
O
RF0~RF3
O
I
RES
TEST
I

ROSC PWM1/DAC
I O
Connect resistor to VDD pad to generate speech or melody playing clock source. While speech or melody is active , PWM1/DAC is speaker direct driving output or DAC output controlled by voice output file. While speech or melody is active, PWM2 is another speaker direct driving output. External serial memory address write clock for voice extension (W536120T only). The "Tri-sate serial bus" mask option can use tri-sate WRP pad while external voice ROM is not available. Default that mask option is disabled and fixes WRP pad state while external voice is not enabled to get chip low power consumption. External serial memory address read clock for voice extension. (W536120T only).The pad state is same as WRP pad depended on "Tri-sate serial bus" mask option. External serial memory data in/out for voice extension (W536120T only).The pad state is same as WRP pad depended on "Tri-sate serial bus" mask option. Dedicated LCD segment output pads. LCD segment output pads, and can be shared as general output by register LCDM3 bit 1. Default function is segment pad. LCD segment output pads, and can be shared as general input by register LCDM3 bit 0. Default function is segment pad and PM5.1=0 to inhibit LCD waveform abnormal. LCD segment output pads, and can be shared as general output by register LCDM2 bit 0. Default function is segment pad. LCD segment output pads, and can be shared as general input by register LCDM2 bit 1. Default function is segment pad and PM5.0=0 to inhibit LCD waveform abnormal. LCD segment output pads, and can be shared as general input/output by register LCDM2 bit 2. PM4 register is used to select input or output while shared I/O function is active. Default function is segment pad and PM4.3=0 to inhibit LCD waveform abnormal. LCD segment output pads, and can be shared as general input/output by register LCDM2 bit 3. PM4 register is used to select input or output while shared I/O function is active. Default function is segment pad and PM4.2=0 to inhibit LCD waveform abnormal.
PWM2 WRP (5)
O O
RDP (5)
O
SPDATA (5)
I/O
SEG0-SEG39 SEG40/PORTN.0 SEG43/PORTN.3 SEG44/PORTM.0 SEG47/PORTM.3 SEG48/PORTL.0 SEG51/PORTL.3 SEG52/PORTK.0 SEG55/PORTK.3 SEG56/PORTJ.0 SEG59/PORTJ.3
O O/O
O/I
O/O
O/I
O/IO
SEG60/PORTI.0 SEG63/PORTI.3
O/IO
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Publication Release Date:Sep 2000 Revision A7

COM0-COM15
O
LCD common signal output pads either 1/32 duty or 1/16 duty. The LCD frame rate is controlled by LCDM1 register, and default value LCDM1=0111b with 64Hz frame rate. LCD common signal output pads while 1/32 duty is active. The LCD frame rate is controlled by LCDM1 register, and default value LCDM1=0111b with 64Hz frame rate. LCD common signal output pads, or shared as general output by register LCDM3.2 when in 1/16 duty mode. Default function is common function. LCD common signal output pads, or shared as general input by register LCDM3.2 when in 1/16 duty mode. Default function is common function and PM5.2=0 to inhibit LCD waveform abnormal. Connection terminal for voltage double capacitor with 0.1uF. The DH2 connects to capacitor positive node and DH1 negative node if polar capacitor is used. LCD COM/SEG output driving voltage. Need an external 0.1uF capacitor to every pad terminal. Voltage regulator output pad. An external capacitor is a must. Output level can be controlled from 0~Fh by LCDM4 register. If internal pump is enabled (LCDM3.3=0 and default value), LCD operating voltage (VLCD) will be 4*V2 or 5*V2 depending on 1/4 bias or 1/5 bias. A limitation should be noted that VLCD must be higher than (VDD-0.5v) to avoid chip leakage current. While external reference voltage is selected (LCDM3.3=1), V2 pad input voltage can not be over 1.5 Volt to inhibit chip damage. Power ground for PWM or DAC playing output. Power ground. Power ground Power source for PWM or DAC playing output. Power ground. Power source.
COM16-COM23
O
COM24/PORTP.0 COM27/PORTP.3 COM28/PORTO.0 COM31/PORTO.3 DH1, DH2 (6)
O/O
O/I
O
V3 ~ V6 (6)
O
V2 (6)
I/O
VSSP VSSA(7) VSS VDDP VDDA(7) VDD
I I I I I I
(4) RD1~3 are shared as RDP/SPDATA/WRP to interface with W55XXX @W536030T/060T (5) @W536120T only (6) 0.1uF is default value, and capacitor value should be larger than 0.1uF if LCD dot size over 0.5mm*0.5mm. (7) External application circuit should connect together, please refer to APPLICATION CIRCUIT. To sure chip operation properly, please bond all VDDP,VDDA, VDD,VSSP,VSS and VSSA pads and connect VSSP, VSS from chip outside PCB circuit. VSSA and VDDA are for W536120T only -6Publication Release Date:Sep 2000 Revision A7

ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage Temperature RATING -0.3 to +7.0 -0.3 to +7.0 120 0 to +70 -55 to +150 UNIT V V mW C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC CHARACTERISTICS
(VDD-VSS = 3.0V, No load, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25 C, STN LCD panel on with dot size 0.5mm*0.5mm; unless otherwise specified) PARAMETER Op. Voltage Op. Current (No Load, no Voice, No Melody) Hold Mode Current (No Load, LCD OFF) Hold Mode Current (No load, LCD ON) Stop Mode Current RDP/WRP Output High Current RDP/WRP Output low Current Input Low Voltage Input High Voltage Port RA, RB Output Low Voltage Port RA, RB Output High Voltage Pull-up Resistor RES Pull-up Resistor PWM1/2 Source Current (8) (RLOAD =8 between PWM1 And PWM2 ) PWM1/2 Sink Current (8) (RLOAD =8 between PWM1 And PWM2 ) ISPL SYM. VDD IOP1 CONDITIONS Dual clock with crystal Dual clock with RC type Sub-clock only, LCD off Sub-clock only, LCD on Sub-clock active only Sub-clock active only LCD auto off Vout=2.7V Vout=0.4V IOL = 2.0 mA IOH = -2.0 mA Port RC, RD Volume Option =00 Volume Option =01 Volume Option =10 Volume Option =11 Volume Option =00 Volume Option =01 Volume Option =10 Volume Option =11 -7VSS 0.7 2.4 200 50 300 100 -20 -70 -110 -135 20 70 110 135 Publication Release Date:Sep 2000 Revision A7 MIN 2.4 TYP 600 600 40 70 6 MAX 5.5 700 700 50 90 10 70 1 -0.8 0.8 0.3 1 0.4 400 200 UNIT V uA
IOP2 IOP3 IOP4 IoH1 IoL1 VIL VIH VABL VABH RCD RRES ISPH
uA uA uA mA mA VDD VDD V V K K mA
mA

DAC output Current LCD Supply Current COM/SEG On Resistor V2 Pad Output Voltage V2 Pad Output Deviation (9) V2 Pad Voltage Step V6 Pad Output Voltage (LCD's VLCD depended on LCDM4 register ) (9)
IDAC ILCD RON VRR VD1 VR2 VLCD
VDD=3v, RL=100ohm No Load, All Seg. ON IOH = 50 A Depended on LCDM4 No Load LCDM4 increased 1 1/4 Bias & no load 1/5 Bias & no load
-4 0.7
-5 50 5K
-6 10K 1.45 5
mA A V % mV V
50 3.8 * V2 4.75 * V2 3.85 * V2 4.8 * V2 3.9 * V2 4.85 * V2 1.5
V2 input voltage VEXT LCDM3.3=1 V (8) PWM current deviation will be 20%. (9) VLCD deviation is governed by LCD dot size. More larger LCD dot will get larger deviation.
AC CHARATERISTICS
(VDD-VSS = 3.0V, No load, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25 C, STN LCD on with dot size 0.5mm*0.5mm; unless otherwise specified) PARAMETER SYM. CONDITIONS MIN. TYP. MAX. UNIT Sub-clock Frequency FSUB Crystal type and X32IN 32768 Hz and X32O with 17pF external cap. Main-clock Frequency FM RC type/Crystal type 400K 4M Hz Chip Operation Frequency FOSC 32768 Hz SCR0.0=1,FSYS=FSUB 4M SCR0.0=0;FSYS= FMAIN 400K Instruction Cycle Time TCYC One machine cycle 4/FOSC S Reset Active Width TRAW FOSC = 32.768 KHz 1 S Interrupt Active Width TIAW FOSC = 32.768 KHz 1 S Main clock RC frequency FRXIN 1M Hz RXIN =680K 2M (10) RXIN =330K 3M RXIN =200K 4M RXIN =130K Sub-Clock Ring Oscillator FRSUB 32 KHz RSUB=680K Sub-Clock Oscillation 0.8 1 S FSTOP RSUB=680K Stable Time @ Cold Start 10 % Frequency Deviation of f(3V) - f(2.4V) f f main-clock FRXIN 2MHz f(3V) 15 % Frequency Deviation of f(3V) - f(2.4V) f main-clock FRXIN = 3MHz f f(3V) 20 % Frequency Deviation of f(3V) - f(2.4V) f main-clock FRXIN =4 MHz f f(3V) ROSC Frequency FROSC 3 MHz ROSC=680K 7.5 % Frequency Deviation of f(3V) - f(2.4V) f FROSC = 3MHz f f(3V) Frame frequency FLCD LCDM1=0111 b(default) 64 Hz (10)The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor Publication Release Date:Sep 2000 -8Revision A7

Iop Vs. Main clock RC mode
1000 800 600 400 Iop (uA) 200 0
3V 4. 5V
1
2
3
4
Freq (MhZ)
Oscillation Freq Vs. Sub-Clock
44 40 36
3V 4. 5V
Fsub (KhZ) 32
28 24 20 560 620 680 750 820 1K Rsub (Kohm)
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Publication Release Date:Sep 2000 Revision A7

Main Freq Vs. Rxin
6 5 4
Fmain 3 (MhZ)
2 1 0 130 150 160 200 330 680 2K 3K
2.4V 3v 4.5V 5.5V
RXIN (Kohm)
Voice Operating Freq. Vs. ROSC
Freq (MhZ)
4. 5 4 3. 5 3 2. 5 2 470 560 680 910
ROSC (Kohm)
3V 4. 5V
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Publication Release Date:Sep 2000 Revision A7

APPLICATION CIRCUIT--1: Sub clock with RC mode
VLCD> (VDD-0.5v) Panel COM0~31 SEG0~63
VDDP
RA0~3 RB0~3 RC0~3 RD0~3 RE0~3 RF0~3 VDD ( 2) * R5 RES
470
(*3)
PWMP/DAC
Battery
C9 VDDP
W536xxxT
V6 V5
PWMN DH1 DH2 + C1 (*1) C5 C4 C3 C2
C11 C10
R4 VDD VDDA R1 ROSC R3 XIN
C6
V4 X32IN V3 R2 X32O VSS V2
VSSA
VSSP
Component Value
C1~C6 0.1uF
C7,C8 -
C9,C10 0.1uF
C11 1uF
R1 680K
R2 680K
R3 680Kohm/1Mhz 330Kohm/2Mhz 200Kohm/3Mhz 130Kohm/4Mhz
R4 100
Note:
(1) C1~C6 depends on LCD panel dot size. (2) Option R5 equals to 100 if high noise immunity is needed. (3) For DAC option application. (4) To sure chip operation properly, please bond all VDDP, VDDA,VDD, VSSP,VSS and VSSA pads. VSSA and VDDA are for W536090T/120T only - 11 Publication Release Date:Sep 2000 Revision A7

APPLICATION CIRCUIT--- 2 : Sub clock with Crystal mode
VLCD> (VDD-0.5v) Panel COM0~31 SEG0~63
VDDP
RA0~3 RB0~3 RC0~3 RD0~3 RE0~3 RF0~3 VDD * ( 2) R5 RES C9
Battery
470
(*3)
PWMP/DAC
VDDP
W536xxxT
V6 V5
PWMN DH1 DH2 C1
C11 C10
R4 VDD VDDA R1 ROSC R3 C7 XIN
+
-
C6 (*1) C5 C4 C3 C2
V4 X32IN 32.768kHz C8 X32O VSS VSSA VSSP V3 V2
Component Value
C1~C6 0.1uF
C7,C8 15~20pF
C9,C10 0.1uF
C11 1uF
R1 680K
R2 -
R3 680Kohm/1Mhz 330Kohm/2Mhz 200Kohm/3Mhz 130Kohm/4Mhz
R4 100
Note:
(1) C1~C6 depends on LCD panel dot size. (2) Option R5 equals to 100 if high noise immunity is needed. (3) For DAC option application. (4) To sure chip operation properly, please bond all VDDP, VDDA,VDD, VSSP,VSS and VSSA pads. VSSA and VDDA are for W536090T/120T only Publication Release Date:Sep 2000 Revision A7
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